`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:57:11 05/26/2012
// Design Name:   top
// Module Name:   D:/my_xlinx/xilinx/last_trial/TB.v
// Project Name:  last_trial
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: top
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TB;

	// Inputs
	reg clk;
	reg rst;
	reg rx;

	// Outputs
	wire tx;
	wire [3:0] SpyOpc;
	wire [7:0] SpyUxData;
	wire [7:0] SpyFiData;
	wire [3:0] SpyChrData;
	wire TopTestLed;

	// Instantiate the Unit Under Test (UUT)
	top uut (
		.clk(clk), 
		.rst(rst), 
		.rx(rx), 
		.tx(tx), 
		.SpyOpc(SpyOpc), 
		.SpyUxData(SpyUxData), 
		.SpyFiData(SpyFiData), 
		.SpyChrData(SpyChrData), 
		.TopTestLed(TopTestLed)
	);

	reg [39:0] data1;
	
	always #1 clk=~clk;
	
	
	
parameter CTUNE = 16'h1458;  //parameter where to control the baud speed;
parameter WIDTH = 16;        //parameter to control the counter

reg [(WIDTH-1):0] count;
reg ddsclk;
integer i;
	
always @(posedge clk) begin

   if(rst) begin
     count <= {WIDTH{1'b0}};
     ddsclk <= 1'b0;
   end else if(count==CTUNE) begin
     ddsclk <= ~ddsclk;
     count <= {WIDTH{1'b0}};
   end else
     count <= count + 1'b1;
end

	initial begin:stopat
	#2000000;
	$finish;
	end

	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 1;
		rx = 1;
		i=0;
		data1[9:0]	={1'b0,8'd49,1'b1};
		data1[19:10]={1'b0,8'd49,1'b1};
		data1[29:20]={1'b0,8'd49,1'b1};
		data1[39:30]={1'b0,8'd49,1'b1};      
		// Add stimulus here
		# 50 rst =0;
	end

	
always@(posedge ddsclk)
			begin
			rx=data1[i];
			i=i+1;
			if(i==40) i=0;
			end
      
endmodule

